By Himanshu Bhatnagar
The emphasis of this publication is on real-time program of Synopsys instruments, used to wrestle a variety of difficulties obvious at VDSM geometries. Readers should be uncovered to an efficient layout method for dealing with complicated, sub-micron ASIC designs. value is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to structure, actual synthesis, and static timing research. At every one step, difficulties comparable to every part of the layout movement are pointed out, with ideas and work-around defined intimately. additionally, an important concerns similar to format, consisting of clock tree synthesis and back-end integration (links to format) also are mentioned at size. in addition, the ebook includes in-depth discussions at the foundation of Synopsys know-how libraries and HDL coding types, detailed in the direction of optimum synthesis answer.
goal audiences for this e-book are practising ASIC layout engineers and masters point scholars venture complicated VLSI classes on ASIC chip layout and DFT techniques.
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Extra resources for Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime®
Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime® by Himanshu Bhatnagar